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thanoozm
New User
Joined: 23 May 2007 Posts: 26 Location: hyderabad
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Hi ,
Divide instruction is failing in assembler program.
I have moved X`0000D221` into register R5.
SLA R5,5
LA R4,0
D R4,F`12` – this instruction is giving abend.
Thanks
Thanooz. |
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Robert Sample
Global Moderator
Joined: 06 Jun 2008 Posts: 8700 Location: Dubuque, Iowa, USA
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Okay, you didn't tell us which abend you're getting. You didn't give us any of the diagnostic data put out by the system. You didn't give us anything but three lines of assembler.
So just what do you expect us to do with so little? This isn't psychic day. If it was, I'd suggest line 379 is where your problem is. |
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PeterHolland
Global Moderator
Joined: 27 Oct 2009 Posts: 2481 Location: Netherlands, Amstelveen
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The SLA instruction i dont understand.
You load the uneven register with a value,
you zero the even register
and then divide the even register with a register or a storage value. |
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thanoozm
New User
Joined: 23 May 2007 Posts: 26 Location: hyderabad
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Hi Robert,
System is giving S0c9 error. SYSabend dump is 235,00 pages. I will attach that.
Thanks,
thanooz. |
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Garry Carroll
Senior Member
Joined: 08 May 2006 Posts: 1205 Location: Dublin, Ireland
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First thing that leaps to mind is the absence of an equals sign on the divide....
Peter:
The SLA is a Shift Left Single. The POP shows a different way of doing this which also suggests that the OP's way may be questionable. Loading the even-register with the value and SRDA 27 bits might be safer?
Garry. |
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Robert Sample
Global Moderator
Joined: 06 Jun 2008 Posts: 8700 Location: Dubuque, Iowa, USA
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You certainly don't need to attach the whole dump -- there is more diagnostic data produced than just a dump! Giving us the abending instruction, registers and PSW for example would be a good start. From the POP:
Quote: |
Fixed-Point-Divide Exception
A fixed-point-divide exception is recognized when
any of the following is true:
1. In signed or unsigned binary division when the
result is defined to be 32 bits, the divisor is zero,
or the quotient cannot be expressed as a 32-bit
signed or unsigned, respectively, binary integer.
2. In signed or unsigned binary division when the
result is defined to be 64 bits, the divisor is zero,
or the quotient cannot be expressed as a 64-bit
signed or unsigned, respectively, binary integer.
3. The result of CONVERT TO BINARY cannot be
expressed as a 32-bit signed binary integer for a
32-bit result or as a 64-bit signed binary integer
for a 64-bit result.
In the case of division, the operation is suppressed.
The execution of CONVERT TO BINARY (CVB) is
completed by ignoring the leftmost bits that cannot
be placed in the register. The execution of CONVERT
TO BINARY (CVBG) is suppressed.
The instruction-length code is 1, 2, or 3. |
Since you're not doing a CVB, it's probably not that. I would expect, most likely, that location x'12' from your base register contains x'00000000' which would definitely cause a S0C9 ABEND. |
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thanoozm
New User
Joined: 23 May 2007 Posts: 26 Location: hyderabad
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Hi Robert,
I have tried to display the value before divide instruction. It has displayed correct value '00000691'. |
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Robert Sample
Global Moderator
Joined: 06 Jun 2008 Posts: 8700 Location: Dubuque, Iowa, USA
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The D instruction -- what is the generated machine code for 5 instructions before and after it? This is listed on the assembler output to the left of the mnemonic and operands.
Also, note that there is absolutely no question about the register containing a valid value -- this abend occurs because you are dividing the number in the register by zero (for example). So telling us the register has x'00000691' is not providing any useful data to us. |
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thanoozm
New User
Joined: 23 May 2007 Posts: 26 Location: hyderabad
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Hi Robert,
Listing before 5 instructions.
Code: |
D501 B236 300E 00236 00262 210 CLC DATEIN,=H'0'
4780 B224 00224 211 BE DT2
1B55 212 SR R5,R5
1B44 213 SR R4,R4
BF53 B236 00236 214 ICM R5,3,DATEIN
8850 0005 00005 215 SRL R5,5
4140 0000 00000 216 LA R4,0
5D40 3008 0025C 221 D R4,=F'12'
4A50 3010 00264 222 AH R5,=H'70'
1244 223 LTR R4,R4
4780 B1E0 001E0 224 BZ DT1
0650 225 BCTR R5,R0
4140 000C 0000C 226 LA R4,12
4E40 B24C 0024C 227 DT1 CVD R4,PACK8
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Bill O'Boyle
CICS Moderator
Joined: 14 Jan 2008 Posts: 2501 Location: Atlanta, Georgia, USA
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The proper way to load the odd-register prior to issuing a D/DR instruction and preserve the sign (positive or negative, regardless) is to load the even register first and then shift right 32-Bits into the adjacent odd-register. Example -
Code: |
L R4,=F'-120' LOAD WITH F'-120'
SRDL R4,32 SHIFT 32-BITS/PRESERVE SIGN
D R4,=F'12' DIVIDE WITH RSLT IN R5 (REMAINDER IF ANY IN R4)
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Bill |
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Garry Carroll
Senior Member
Joined: 08 May 2006 Posts: 1205 Location: Dublin, Ireland
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Dear God!
What part of
Quote: |
You certainly don't need to attach the whole dump |
is not understood??
Also, not everyone can (or will) read atachments - as has been so often stated.
Garry. |
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Robert Sample
Global Moderator
Joined: 06 Jun 2008 Posts: 8700 Location: Dubuque, Iowa, USA
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I suspect your registers are getting out of whack somewhere. Your code has the divide instruction generating as 5D40 3008, so register 3 offset 008 is being used to pull in the F'12' Yet your dump shows
Code: |
GENERAL PURPOSE REGISTER VALUES
0-3 00001000 00A71000 00A7E970 00000064
4-7 00000690 80E212C0 230158E0 230158B8
8-11 00000000 00A74752 00A747FA 7F391018
12-15 86606000 00A7E9F4 86606036 00000000 |
I really doubt memory location 00000072 contains your F'12' -- I don't know what it does contain, but probably not an F'12'.
It's also interesting that instructions 217 - 220 are not present in the listing you posted. |
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Bill O'Boyle
CICS Moderator
Joined: 14 Jan 2008 Posts: 2501 Location: Atlanta, Georgia, USA
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Once the ICM has been issued and R5 is greater than F'0', but it is less than F'16' (X'00000010'), when you issue an SRL R5,5 (same as D R5,=F'16'), the result in R5 will be F'0'. This is how the S0C9 is being raised.
Let's say R5 equals F'15' (B'00001111'). When you shift-right 5-Bits, the B'00001111' becomes B'00000000'.
Bill |
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thanoozm
New User
Joined: 23 May 2007 Posts: 26 Location: hyderabad
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Hi Bill,
That is correct, my value in R5 is `0000D221` after right shift it will become `00000691`.
I am geting correct value upto that. |
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thanoozm
New User
Joined: 23 May 2007 Posts: 26 Location: hyderabad
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Hi Robert,
I am not able to see the adress off R3 in dump, Please let me know where you seen.
thanks,
Thanooz. |
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Bill O'Boyle
CICS Moderator
Joined: 14 Jan 2008 Posts: 2501 Location: Atlanta, Georgia, USA
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thanoozm wrote: |
Hi Bill,
That is correct, my value in R5 is `0000D221` after right shift it will become `00000691`.
I am geting correct value upto that. |
Oops, my mistake, should be divide by F'32' and get a F'0' when R5 is less than F'32', but the R5 value exceeds this.
I'm on medication after dental surgery, so I was off by just a little "BIT"
Bill |
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Bill O'Boyle
CICS Moderator
Joined: 14 Jan 2008 Posts: 2501 Location: Atlanta, Georgia, USA
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The sub-program's base register (R3) may be corrupted.
Are you loading R3 from R15 when the sub-program gains control?
As an alternative, instead of using a literal F'12' with the D instruction, load a spare register (R10 for example), with an F'12' (LA R10,12). Then change your D to a Divide Register (DR R4,R10) and see if that makes a difference.
Is this D always causing an S0C9 or does it work sometimes?
Bill |
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thanoozm
New User
Joined: 23 May 2007 Posts: 26 Location: hyderabad
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Hi Bill,
It worked some times correctly. Today it is giving problem.
thanks,
Thanooz. |
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PeterHolland
Global Moderator
Joined: 27 Oct 2009 Posts: 2481 Location: Netherlands, Amstelveen
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This is what i should do :
Code: |
L R6,BLOCK LOAD BLOCKSIZE
SRDA R6,32 PUT IN R7, CLEAR R6
D R6,INLRECL DETERMINE # OF ENTRIES
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Robert Sample
Global Moderator
Joined: 06 Jun 2008 Posts: 8700 Location: Dubuque, Iowa, USA
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Thanooz: in your dump1.txt file, page 27, line 1472 has the first TCB (Task Control Block); the register values are immediately after the TCB offsets and data values. |
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thanoozm
New User
Joined: 23 May 2007 Posts: 26 Location: hyderabad
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Hi All,
Thanks for your help. I have changed register loading, now it is working fine.
Thanks to robert and bill. |
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thanoozm
New User
Joined: 23 May 2007 Posts: 26 Location: hyderabad
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Hi Robert,
Where can i see the memory location 00000072 and it's values. I am searching for that and i didn't find. I find the R3 value and i couldn't find the memory value, This for know the things.
problem is resolved, thanks for your help.
Thanks,
Thanooz. |
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Robert Sample
Global Moderator
Joined: 06 Jun 2008 Posts: 8700 Location: Dubuque, Iowa, USA
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Low memory locations are reserved for use by the operating system -- using location 00000072 should only be done by the system; if your registers are pointing there then it is a problem. You usually don't see them in a dump since they are rarely relevant to an application abend. |
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PeterHolland
Global Moderator
Joined: 27 Oct 2009 Posts: 2481 Location: Netherlands, Amstelveen
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Well you can access locations like that, e.g. the CVT.
But its readable not writeable. |
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dick scherrer
Moderator Emeritus
Joined: 23 Nov 2006 Posts: 19243 Location: Inside the Matrix
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Hello,
So, unless the code references system data areas (i.e. control blocks), 72 is not going to be a proper address for the code to reference.
However, registers contain "things" other than addresses. . . Length, count, displacement, etc. . . |
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