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BC, BCR, BRC, BRCL performance

 
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steve-myers

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PostPosted: Fri Dec 23, 2016 7:44 am    Post subject: BC, BCR, BRC, BRCL performance
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Branch on Condition chapter in z/Architecture Principles of Architecture. I particularly notice "When the M1 and R2 fields of BRANCH ON CONDITION (BCR) are all ones and all zeros, respectively, a serialization and checkpoint-synchronization function is performed," and "Execution of BCR 15,0 (that is, an instruction with a value of 07F0 hex) may result in significant performance degradation. To ensure optimum performance, the program should avoid use of BCR 15,0 except in cases when the serialization or checkpoint-synchronization function is actually required." It has occurred to me all executions of a BC, BCR, BRC or BRCL instruction with a non-zero mask should be performing a serialization function to ensure the branch decision is using the most recent condition code. POP does not explicitly say this, though I have to think it must work this way.

I wish someone with a deeper understanding of the hardware than me can confirm or repute this idea. I've known about the serialization issue with BCR for a long time, but never really extended this thought in the sense of it being a generalization.

A related question is, if the mask is all 1s, why bother with serialization? You're going to branch by definition, so you don't need the condition code!

The CPU Serialization chapter does not really provide any guidance on this issue beyond what I can get from the discussion in the first link.
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