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Jimy Carol
New User
Joined: 31 Aug 2012 Posts: 25 Location: Australia
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Hi ,
I am facing a strange problem with MVCL instruction , While execution of a program I found the below behavior of MVCl instruction which ultimately casuing error in output .
Register values before execution of MVCL :
R0=3B8A8EA4 R1=0000000A
R14=3B8B1079 R15=0000000A
Data at R14 (3B8B1079) = versionabc
Register values after execution of MVCL
R0=3B8A8EAE R1=00000000
R14=3B8B1083 R15=00000000
There was no data copied to R0 location , After execution it has low values at r0 location .
The data for sending register r14 comes from a pds file .
Please throw some light as on why this is happening .
Regards
carol |
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enrico-sorichetti
Superior Member
Joined: 14 Mar 2007 Posts: 10873 Location: italy
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not enough info posted! |
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Bill O'Boyle
CICS Moderator
Joined: 14 Jan 2008 Posts: 2501 Location: Atlanta, Georgia, USA
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I understand your post is regarding MVCL, but the data-length is only 10. Couldn't you use an MVC instead, with a hard-coded length of 10 or as an Executed MVC? Seems like a waste of resources.... |
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enrico-sorichetti
Superior Member
Joined: 14 Mar 2007 Posts: 10873 Location: italy
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still would be interesting to find out the reason for the not working situation |
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PeterHolland
Global Moderator
Joined: 27 Oct 2009 Posts: 2481 Location: Netherlands, Amstelveen
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And why would you use R14,R15 as source? You got the same result with using another register pair? |
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Bill O'Boyle
CICS Moderator
Joined: 14 Jan 2008 Posts: 2501 Location: Atlanta, Georgia, USA
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Dick,
An MVCL uses an even/odd set of registers for Operands 1/2.
The OP is correct by loading the RECEIVING address into R0 and the RECEIVING length into R1. R14 contains the SENDING address and R15 contains the SENDING length.
From what was posted, R1 and R15 contain the correct length (F'10') and we can only assume that the addresses in R0 and R14 are correct.
If the R1 length was less than the R15 length, then a pad-character (other than a X'00'), needs to be inserted in the high-order of R15, usually via an ICM, but that's not the case, because they're equal.
MVCL are often used with R0/R1 and R14/R15 (at least, IMHO). |
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dick scherrer
Moderator Emeritus
Joined: 23 Nov 2006 Posts: 19244 Location: Inside the Matrix
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Thanks Bill,
I don't know what i was thinking but a bit later realized i was out in left field somewhere . . . So i deleted my bit of mis-information . . .
Thanks for the clarification
d |
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Bill O'Boyle
CICS Moderator
Joined: 14 Jan 2008 Posts: 2501 Location: Atlanta, Georgia, USA
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Carol,
I have to ask the obvious because we don't see anything wrong with your register usage.
After the MVCL, are you looking at address 3B8A8EAE for the expected data?
You need to look at address 3B8A8EA4.... |
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enrico-sorichetti
Superior Member
Joined: 14 Mar 2007 Posts: 10873 Location: italy
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Very good guess Bill |
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Bill Woodger
Moderator Emeritus
Joined: 09 Mar 2011 Posts: 7309 Location: Inside the Matrix
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The only way the MVCL wouldn't work would be with "destructive overlap", which you don't have. So it worked. You could check the Condition Code to satisfy yourself.
Good shot Mr Bill. |
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PeterHolland
Global Moderator
Joined: 27 Oct 2009 Posts: 2481 Location: Netherlands, Amstelveen
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Very nice, Bill. |
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Jimy Carol
New User
Joined: 31 Aug 2012 Posts: 25 Location: Australia
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Bill O'Boyle wrote: |
Carol,
I have to ask the obvious because we don't see anything wrong with your register usage.
After the MVCL, are you looking at address 3B8A8EAE for the expected data?
You need to look at address 3B8A8EA4.... |
Sorry for the late reply ..could'nt join the forum to see the discussion . I was wrong then as you correctly pointed the mistake i was doing to see the wrong address in R0 .
Thanks all for joining and Improving my knowledge about assembler . |
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